A test system and corresponding method is described in U.S. Pat. No. 5,280,237.
Parasitic transistors accessed through the pins of the IC under consideration are determined therein, such transistors being formed in the IC by the diodes between the substrate and ground. These diodes are parasitic diodes. The resulting transistors thereby formed are identified therein as parasitic transistors or lateral transistors.
The transistor measurements are carried out in the so-called grounded emitter configuration, in which the emitter of the transistor is connected to the ground terminal of the tester. In this method, the base of the transistor, which is the GND pin (ground pin) of the IC, is not connected to ground, as is usually the case, but instead a base voltage suitable to turn on the transistor is applied to it. Two signal pins of the IC are connected as emitter and collector respectively. The diodes between GND and the signal pins respectively form the emitter and collector diodes of the transistor. The collector current is measured. The transistor under test is hereinafter called the "test transistor".
The advantage of this method over previous test methods, for example node impedance measurements, is the improved ability to make reliable verification of the proper connection of the pins of IC's on complex boards, particularly those with bus structured circuits, where many IC pins are in parallel.
IC's fabricated in bipolar technology such as TTL contain test transistors which lend themselves well to such test methods. Difficulties are however encountered when testing IC's fabricated in CMOS technology, which is increasingly being used. Presently almost all high density IC's are manufactured using CMOS technology.
It transpires that for CMOS IC's even when measuring isolated IC's with open pins (i.e. when they are not connected into a circuit), problems arise which are due to effects topically known i n the literature as "background currents". When a test transistor is measured in a CMOS IC, currents are generated which are significantly higher than the current expected from the test transistor itself. The additional current apparently flowing through the test transistor and referred to hereafter as additional current, is referred to in the literature as "background current". This additional current is highly dependent on IC manufacturing parameters, such as different manufacturers or different batches.
It is difficult or impossible to separate the current due to the test transistor from the additional current. Because the additional current is often significantly higher than the test transistor's current, it is not possible to make reliable deductions about the properties of the test transistor.
If, due to parallel connections between the pins of the IC, several test transistors are in parallel, and the current due to one test transistor is known, it is possible to deduce the number of test transistors from the total current flowing in the parallel circuit, since the test transistors of an IC usually exhibit similar characteristics. If however a very high additional current flows , such deductions about the number of test transistors connected in parallel are impossible.